(Experienced) Walk-In : ASIC & FPGA @ Bangalore
1. ASIC VERIFICATION & DESIGN :
Desired Experience : 2 to 10 Years (Mandatory)
Multiple skills required :
• Expertise in System Verilog & OVM (ASIC).
• Expertise in System Verilog & e-specman (ASIC).
• Expertise in Mixed Signal Verification (ASIC).
• Expertise in Low Power Design Verification (ASIC).
• SOC Verification with 'C' based Verification Environment (ASIC).
Job Location : Hyderabad & Bangalore
2. LOGIC DESIGN
Desired Experience : 3 to 10 Years (Mandatory)
• He/She should be able to come up with microarchitecture of chip/block from high-level architecture.
• Should have expertise in logic design, RTL coding, module level verification and debug, basic understanding on timing closure, constraints, interacting with backend/DFT teams to close DFT/timing related issues.
Job Location : Hyderabad & Bangalore
3. FPGA ENGINEERS :
Desired Experience : 3 to 8 Years (Mandatory)
Desired Skills :
• Ability to interface with silicon companies and understand their requirements and expectations.
• Rapidly adapt to different design and verification environments
• Coordinate efforts with offshore design and verification teams
• Strong experience using Verilog/VHDL
Job Location : Hyderabad
Qualification for all the software positions : BE / B.Tech / ME / M.Tech / MS
Please Carry (mandatory) :
• Updated Resume Copy
• Photo ID Proof
• Latest Pay Slips
• Academics, Experience letters
• Passport Size Photograph
Walk-In Date : On 20th, 21st August 2011 : 10 AM to 3 PM
Walk-In Venue :
Grand Krishna Rooms,
#77, Hosur Main Road,
Near Ayyappa Temple, Madiwala,
Bangalore-560068
Contact Person : Praveen Kumar Vemula
Contact Number : +91-80-25525723/4
1. ASIC VERIFICATION & DESIGN :
Desired Experience : 2 to 10 Years (Mandatory)
Multiple skills required :
• Expertise in System Verilog & OVM (ASIC).
• Expertise in System Verilog & e-specman (ASIC).
• Expertise in Mixed Signal Verification (ASIC).
• Expertise in Low Power Design Verification (ASIC).
• SOC Verification with 'C' based Verification Environment (ASIC).
Job Location : Hyderabad & Bangalore
2. LOGIC DESIGN
Desired Experience : 3 to 10 Years (Mandatory)
• He/She should be able to come up with microarchitecture of chip/block from high-level architecture.
• Should have expertise in logic design, RTL coding, module level verification and debug, basic understanding on timing closure, constraints, interacting with backend/DFT teams to close DFT/timing related issues.
Job Location : Hyderabad & Bangalore
3. FPGA ENGINEERS :
Desired Experience : 3 to 8 Years (Mandatory)
Desired Skills :
• Ability to interface with silicon companies and understand their requirements and expectations.
• Rapidly adapt to different design and verification environments
• Coordinate efforts with offshore design and verification teams
• Strong experience using Verilog/VHDL
Job Location : Hyderabad
Qualification for all the software positions : BE / B.Tech / ME / M.Tech / MS
Please Carry (mandatory) :
• Updated Resume Copy
• Photo ID Proof
• Latest Pay Slips
• Academics, Experience letters
• Passport Size Photograph
Walk-In Date : On 20th, 21st August 2011 : 10 AM to 3 PM
Walk-In Venue :
Grand Krishna Rooms,
#77, Hosur Main Road,
Near Ayyappa Temple, Madiwala,
Bangalore-560068
Contact Person : Praveen Kumar Vemula
Contact Number : +91-80-25525723/4
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